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9fg430 idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 f our output dif f er ential f r equenc y gener a tor for pcie gen3 and qpi 1 da t asheet general description:the 9fg430 is a f requency timing gener ator that pro vides 4 hcsl diff erential output pairs . these outputs suppor t pci-express gen3, and qpi applications . the par t suppor ts spread spectr um and synthesizes several additional output frequencies from eithera 14.31818 mhz crystal, a 25 mhz crystal or reference input clock. the 9fg430 also outputs a copy of the reference clock. complete control of the device is available via strapping pins or via the smbus inteface. recommended application: 4 output diff erential f requency gener ator f or pcie gen3 and qpi output features:? 4 - 0.7v current mode differential hcsl output pairs ? 1 - 3.3v l vttl ref output features/benefits:? pin-to-pin with 9fg104d/easy upgrade to pcie gen3 ? generates common frequencies from 14.318 mhz or 25mhz; single part supports mulitple applications ? provides copy of reference output; eleminates need foradditional crystal or oscillator ? unused outputs may be disabled in hi-z; save systempower ? device may be configured by smbus and/or strap pins;can be used in systems without smbus key specifications:? cycle-to-cycle jitter: < 50ps with 25mhz input ? output-to-output skew: <50ps ? phase jitter: pcie gen3 < 1ps rms ? phase jitter: qpi 9.6gb/s < 0.2ps rms ? 10 ppm synthesis error with 25mhz input and spread off functional block diagram stop logic xin/clkin x2 dif(3:0) control logic spread fs(2:0) sdata sclk sel14m_25m# dif_stop# programmable spread pll 4 iref osc r e f o u t
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 2 pin configuration po wer gr oups vdd gnd 3 4 9,21 10,20 28 27 iref, analog vdd, gnd for pll core description pin num ber refout, digital inputs dif outputs frequency select table sel14m_25m# (fs3) fs2 fs1 fs0 output (mhz) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.67 0 1 1 0 333.33 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.67 1 1 1 0 333.33 1 1 1 1 400.00 xin/clkin 1 28 vdda x2 2 27 gnda vdd 3 26 iref gnd 4 25 vfs0 refout 5 24 vfs1 vfs2 6 23 dif_0 dif_3 7 22 dif_0# dif_3# 8 21 vdd vdd 9 20 gnd gnd 10 19 dif_1 dif_2 11 18 dif_1# dif_2# 12 17 ^sel14m_25m# sdata 13 16 vspread sclk 14 15 dif_stop# 9fg430 ^ indicates internal 120k pull up v indicates internal 120k pull down
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 3 pin description pin # pin name pin type description 1 xin/clkin in crystal input or reference clock input 2 x2 out crystal output, nominally 14.318mhz 3 vdd pwr power supply, nominal 3.3v 4 gnd pwr ground pin. 5 refout out reference clock output 6 vfs2 in frequency select pin. this pin has an intern al 120k pull down resistor 7 dif_3 out 0.7v differential true clock output 8 dif_3# out 0.7v differential complementary clock out put 9 vdd pwr power supply, nominal 3.3v 10 gnd pwr ground pin. 11 dif_2 out 0.7v differential true clock output 12 dif_2# out 0.7v differential complementary clock ou tput 13 sdata i/o data pin for smbus circuitry, 5v tolerant . 14 sclk in clock pin of smbus circuitry, 5v tolerant. 15 dif_stop# in active low input to stop differential output clocks. 16 vspread in asynchronous, active high input to enable spread sp ectrum functionality. this pin has a 120kohm pull down resistor. 17 ^sel14m_25m# in select 14.31818 mhz or 25 mhz input frequency. thi s pin has an internal 120kohm pull up resistor. 1 = 14.31818 mhz, 0 = 25 mhz 18 dif_1# out 0.7v differential complementary clock ou tput 19 dif_1 out 0.7v differential true clock output 20 gnd pwr ground pin. 21 vdd pwr power supply, nominal 3.3v 22 dif_0# out 0.7v differential complementary clock ou tput 23 dif_0 out 0.7v differential true clock output 24 vfs1 in frequency select pin. 25 vfs0 in frequency select pin. 26 iref out this pin establishes the reference for the differen tial current-mode output pairs. it requires a fixed precision resistor to ground. 475o hm is the standard value for 100ohm differential impedance. other impedances req uire different values. see data sheet. 27 gnda pwr ground pin for the pll core. 28 vdda pwr 3.3v power for the pll core. note: ^ indicates internal 120k pull up v indicates internal 120k pull down
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 4 electrical characteristics - absolute maximum ratin gs parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - input/supply/common pa rameters ta = tcom or tind; supply voltage vdd = 3.3 v +/-5% ; see test loads s for loading conditions. parameter symbol conditions min typ max units notes t com commmercial range 0 70 c 1 t ind industrial range -40 85 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2 v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 sel14m_25m# = 0 25 mhz 1 sel14m_25m# = 1 14.31818 mhz 1 pin inductance l pin 7 nh 1 c in logic inputs, except dif_in 1.5 5 pf 1 c inxtal crystal inputs 6 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1.8 ms 1,2 input ss modulation frequency f modin allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 cycles 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v 1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4 ma 1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for th e smbus to be active ambient operating temperature input current 3 time from deassertion until outputs are >200 mv 4 dif_in input capacitance input frequency f in
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 5 electrical characteristics - current consumption parameter symbol conditions min typ max units notes i dd3.3 vdd, all outputs active @100mhz 80 95 ma 1 i dda3.3op vdda, all outputs active @100mhz 25 30 ma 1 i dd3.3 vdd, all outputs active @400mhz 100 120 ma 1 i dda3.3op vdda, all outputs active @400mhz 25 30 ma 1 i dd3.3pd vdd, all differential pairs driven 75 90 ma 1 i dda3.3pd vdda, all differential pairs driven 25 30 ma 1 i dd3.3pdz vdd, all differential pairs tri-stated 25 30 ma 1 i dda3.3pdz vdda, all differential pairs tri-stated 25 30 ma 1 1 guaranteed by design and characterization, not 100% tested in production. 2 i ref = v dd /(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 . ta = tcom or tind; supply voltage vdd = 3.3 v +/-5% , see test loads for loading operating supply current powerdown current electrical characteristics - output duty cycle, jit ter, and skew characterisitics parameter symbol conditions min typ max units notes duty cycle t dc measured differentially, pll mode 45 55 % 1 skew, output to output t sk3 v t = 50% 50 ps 1 jitter, cycle to cycle t jcyc-cyc 25m input 50 ps 1,3 jitter, cycle to cycle t jcyc-cyc 14.318m input 60 ps 1,3 1 guaranteed by design and characterization, not 100% tested in production. 2 i ref = v dd /(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 . 3 measured from differential waveform 4 duty cycle distortion is the difference in duty cy cle between the output and the input clock when the device is operated in bypass mode. ta = tcom or tind; supply voltage vdd = 3.3 v +/-5% , see test loads for loading electrical characteristics - dif 0.7v current mode differential outputs ta = tcom or tind; supply voltage vdd = 3.3 v +/-5% ; see test loads s for loading conditions. parameter symbol conditions min typ max units notes slew rate trf scope averaging on 1 4 v/ns 1, 2, 3 slew rate matching ? trf slew rate matching, scope averaging on 20 % 1, 2, 4 voltage high vhigh 660 850 1 voltage low vlow -150 150 1 max voltage vmax 1150 1 min voltage vmin -300 1 vswing vswing scope averaging off 300 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 250 550 mv 1, 5 crossing voltage (var) ? -vcross scope averaging off 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset o f v_cross_min/max (v_cross absolute) allowed. the intent is to limit vcross in duced modulation by setting v_cross_delta to be sma ller than v_cross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 (100 differential impedance). 3 slew rate is measured through the vswing voltage ra nge centered around differential 0v. this results in a +/-150mv window around differential 0v. 4 matching applies to rising edge rate of clock / fal ling edge rate of clock#. it is measured in a +/-75 mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calcula te the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling).
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 6 electrical characteristics - phase jitter parameter s ta = t com or t ind; supply voltage vdd = 3.3 v +/-5%, see test loads f or loading conditions parameter symbol conditions min typ max units notes t jphpcieg1 pcie gen 1 86 ps (p-p) 1,2,3,6 pcie gen 2 lo band 10khz < f < 1.5mhz 3 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 3.1 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 1 ps (rms) 1,2,4,5, 6 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.5 ps (rms) 1,5,6 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.3 ps (rms) 1,5,6 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.2 ps (rms) 1,5,6 1 guaranteed by design and characterization, not 100% tested in production. 6 applies to all differential outputs phase jitter, qpi/smi 2 see http://www.pcisig.com for complete specs t jphqpi_smi t jphpcieg2 phase jitter, pci express 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 subject to final radification by pci sig. 5 calculated from intel-supplied clock jitter tool v 1.6.3 electrical characteristics - ref-14.318/25 mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values ppm 1 clock period t period 14.318mhz output nominal 69.8413 ns 1,2 clock period t period 25.000mhz output nominal 40 ns 1,2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 rise/fall time t rf1 v ol = 0.4 v, v oh = 2.4 v 0.5 0.8 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc vt = 1.5 v 250 400 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 0 ta = tcom or tind; supply voltage vdd = 3.3 v +/-5% , see test loads for loading 2 all long term accuracy and clock period specificati ons are guaranteed assuming that ref is at 14.31818 or 25.00 mhz
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 7 common recommendations for differential routing dime nsion or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max i nch 1 l2 length, route as non-coupled 50ohm trace 0.2 max i nch 1 l3 length, route as non-coupled 50ohm trace 0.2 max i nch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm diffe rential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differ ential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm diffe rential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differ ential trace 0.225 min to 12.6 max inch 2 output termination and layout information hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing (test load) hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 8 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compati ble 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts termination for cable ac coupled application (figur e 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc 9fgxxx ref output 33 figure 5. ref output test load 5pf zo = 50 ohms
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 9 differential clock tolerances x1 = 25mhz clock periods - differential outputs with spread sp ectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short- term average max +c2c jitter absper max 0 100.00 9.95000 10.00000 10.00000 10.00000 10.05000 ns 1,2 0 125.00 7.95000 8.00000 8.00000 8.00000 8.05000 ns 1,2 0 133.33 7.45000 7.50000 7.50000 7.50000 7.55000 ns 1,2 10 166.67 5.94994 5.99994 6.00000 6.00006 6.05006 ns 1,2 0 200.00 4.95000 5.00000 5.00000 5.00000 5.05000 ns 1,2 6 266.67 3.69998 3.74998 3.75000 3.75002 3.80002 ns 1,2 10 333.33 2.94997 2.99997 3.00000 3.00003 3.05003 ns 1,2 0 400.00 2.45000 2.50000 2.50000 2.50000 2.55000 ns 1,2 clock periods - differential outputs with spread sp ectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short- term average max +c2c jitter absper max 96 99.75 9.94906 9.99906 10.02406 10.02506 10.02603 10.051 03 10.10103 ns 1,2 19 124.69 7.94925 7.99925 8.01925 8.02005 8.02020 8.04020 8 .09020 ns 1,2 96 133.00 7.44930 7.49930 7.51805 7.51880 7.51952 7.53827 7 .58827 ns 1,2 10 166.25 5.94943 5.99943 6.01443 6.01504 6.01510 6.03010 6 .08010 ns 1,2 96 199.50 4.94953 4.99953 5.01203 5.01253 5.01301 5.02551 5 .07551 ns 1,2 -98 266.00 3.69965 3.74965 3.75902 3.75940 3.75903 3.76841 3.81841 ns 1,2 10 332.50 2.94972 2.99972 3.00722 3.00752 3.00755 3.01505 3 .06505 ns 1,2 96 399.00 2.44977 2.49977 2.50602 2.50627 2.50651 2.51276 2 .56276 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. ssc off or ssc +/- 0.25% center spread synthesis error (ppm) 2 all ppm specifications are guaranteed with the assu mption that the ref output is tuned to the exact ta rget xtal frequency. synthesis error (ppm) dif dif measurement window units ssc on -0.5% down spread center freq. mhz center freq. mhz notes notes measurement window units
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 10 differential clock tolerances, x1 = 14.31818mhz clock periods - differential outputs with spread sp ectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short- term average max +c2c jitter absper max 35 100.00 9.94965 9.99965 10.00000 10.00035 10.05035 ns 1,2 -114 125.00 7.95091 8.00091 8.00000 7.99909 8.04909 ns 1,2 35 133.33 7.44974 7.49974 7.50000 7.50026 7.55026 ns 1,2 -104 166.67 5.95062 6.00062 6.00000 5.99937 6.04937 ns 1,2 35 200.00 4.94983 4.99983 5.00000 5.00018 5.05018 ns 1,2 42 266.67 3.69984 3.74984 3.75000 3.75016 3.80016 ns 1,2 -104 333.33 2.95031 3.00031 3.00000 2.99969 3.04969 ns 1,2 35 400.00 2.44991 2.49991 2.50000 2.50009 2.55009 ns 1,2 clock periods - differential outputs with spread sp ectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short- term average max +c2c jitter absper max 199 99.75 9.94906 9.99906 10.02406 10.02506 10.02706 10.05 206 10.10206 ns 1,2 -100 124.69 7.94925 7.99925 8.01925 8.02005 8.01925 8.0392 5 8.08925 ns 1,2 199 133.00 7.44930 7.49930 7.51805 7.51880 7.52029 7.53904 7.58904 ns 1,2 10 166.25 5.94943 5.99943 6.01443 6.01504 6.01510 6.03010 6 .08010 ns 1,2 199 199.50 4.94953 4.99953 5.01203 5.01253 5.01353 5.02603 5.07603 ns 1,2 -140 266.00 3.69965 3.74965 3.75902 3.75940 3.75887 3.7682 5 3.81825 ns 1,2 10 332.50 2.94972 2.99972 3.00722 3.00752 3.00755 3.01505 3 .06505 ns 1,2 199 399.00 2.44977 2.49977 2.50602 2.50627 2.50676 2.51301 2.56301 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. ssc on -0.5% down spread center freq. mhz synthesis error (ppm) measurement window units center freq. mhz measurement window units 2 all ppm specifications are guaranteed with the assu mption that the ref output is tuned to the exact ta rget xtal frequency. ssc off or ssc +/- 0.25% center spread synthesis error (ppm) dif dif notes notes
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 11 general smbus serial interface information for the 9fg430 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the write address dc (h) ? idt clock will acknowledge ? controller (host) sends the begining byte location = n ? idt clock will acknowledge ? controller (host) sends the data byte count = x ? idt clock will acknowledge ? controller (host) star ts sending byte n thr ough byte n + x -1(see note 2) ? idt clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read:? controller (host) will send star t bit. ? controller (host) sends the write address dc (h) ? idt clock will acknowledge ? controller (host) sends the begining bytelocation = n ? idt clock will acknowledge ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address dd (h) ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n + x -1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit idt (sla ve /re ce ive r) t w r ack ack ack ack ack p stop bit x byte index block write operation slave address dc (h ) beginning byte = n w rite start bit controlle r (host) byte n + x - 1 data byte count = x beginning byte n t start bit w r w rite rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit slave address dd (h ) index block read operation slave address dc (h ) beginning byte = n ack ack data byte count = x ack idt (sla ve /re ce ive r) controlle r (host) x byte ack ack
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 12 smbus table: device control register, read/write ad dress (dc/dd) pin # name control function type 0 1 default bit 7 rw pin 17 bit 6 rw pin 6 bit 5 rw pin 24 bit 4 rw pin 25 bit 3 rw off on pin 16 bit 2 rw hardware select software select 0 bit 1 rw driven hi-z 0 bit 0 rw down center 0 notes: 1. these bits reflect the state of the correspondin g pins at power up, but may be written to if byte 0, bit 2 is set to '1'. fs3 is the sel14m_2 5m# pin. smbus table: output enable register pin # name control function type 0 1 default bit 7 1 bit 6 dif_3 en output enable rw disable enable 1 bit 5 dif_2 en output enable rw disable enable 1 bit 4 1 bit 3 1 bit 2 dif_1 en output enable rw disable enable 1 bit 1 dif_0 en output enable rw disable enable 1 bit 0 1 smbus table: output stop control register pin # name control function type 0 1 default bit 7 0 bit 6 dif_3 stop en free run/ stop enable rw free-run stop-ab le 0 bit 5 dif_2 stop en free run/ stop enable rw free-run stop-ab le 0 bit 4 0 bit 3 0 bit 2 dif_1 stop en free run/ stop enable rw free-run stop-ab le 0 bit 1 dif_0 stop en free run/ stop enable rw free-run stop-ab le 0 bit 0 0 reserved reserved reserved reserved reserved 24 25 byte 0 17 6 16 spread enable 1 - enable software control of frequency, spread enable (spread type always software control) dif_stop# drive mode spread type byte 1 -- - - - - - - byte 2 -- - - - - see frequency selection table, page 1 fs3 1 fs2 1 fs1 1 fs0 1 -- reserved reserved reserved
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 13 smbus table: frequency select readback register pin # name control function type 0 1 default bit 7 sel14m_25m# 1 (fs3) state of pin 17 r pin 17 bit 6 fs2 1 state of pin 6 r pin 6 bit 5 fs1 1 state of pin 24 r pin 24 bit 4 fs0 1 state of pin 25 r pin 25 bit 3 spread 1 state of pin 26 r off on pin 16 bit 2 0 bit 1 0 bit 0 0 notes: 1. these bits reflect the state of the correspondin g pins, regardless of whether software programming is enabled or not. smbus table: vendor & revision id register pin # name control function type 0 1 default bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function type 0 1 default bit 7 did7 r - - 0 bit 6 did6 r - - 1 bit 5 did5 r - - 0 bit 4 did4 r - - 0 bit 3 did3 r - - 0 bit 2 did2 r - - 0 bit 1 did1 r - - 1 bit 0 did0 r - - 1 smbus table: byte count register pin # name control function type 0 1 default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 reserved reserved reserved device id = 43 hex byte 3 6 27 45 44 see frequency selection table, page 1 - 16 vendor id -- - - byte 4 - revision id -- - - - - - byte 5 -- - - - - byte 6 writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. -- - - -
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 14 smbus table: reserved register pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: reserved register pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: m/n programming enable pin # name control function type 0 1 default bit 7 m/n_enable m/n prog. enable rw disable enable 0 bit 6 1 bit 5 refout_en refout enable rw disable enable 1 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: pll frequency control register pin # name control function type 0 1 default bit 7 pll n div8 n divider prog bit 8 rw x bit 6 pll n div9 n divider prog bit 9 rw x bit 5 pll m div5 rw x bit 4 pll m div4 rw x bit 3 pll m div3 rw x bit 2 pll m div2 rw x bit 1 pll m div1 rw x bit 0 pll m div0 rw x - byte 10 - the decimal representation of m and n divider in byte 10 and 11 will configure the pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = fxtal x [ndiv(9:0)+8] / [mdiv(5:0)+2]. the user does not need to program these resgisters for standard frequencies. -- m divider programming bit (5:0) -- - - - reserved reserved reserved reserved - reserved -- - 5 - reserved reserved byte 9 - - reserved reserved reserved reserved byte 8 -- - - - - - byte 7 -- - - - - - - reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 15 smbus table: pll frequency control register pin # name control function type 0 1 default bit 7 pll n div7 rw x bit 6 pll n div6 rw x bit 5 pll n div5 rw x bit 4 pll n div4 rw x bit 3 pll n div3 rw x bit 2 pll n div2 rw x bit 1 pll n div1 rw x bit 0 pll n div0 rw x smbus table: pll spread spectrum control register pin # name control function type 0 1 default bit 7 pll ssp7 rw x bit 6 pll ssp6 rw x bit 5 pll ssp5 rw x bit 4 pll ssp4 rw x bit 3 pll ssp3 rw x bit 2 pll ssp2 rw x bit 1 pll ssp1 rw x bit 0 pll ssp0 rw x smbus table: pll spread spectrum control register pin # name control function type 0 1 default bit 7 0 bit 6 pll ssp14 rw x bit 5 pll ssp13 rw x bit 4 pll ssp12 rw x bit 3 pll ssp11 rw x bit 2 pll ssp10 rw x bit 1 pll ssp9 rw x bit 0 pll ssp8 rw x - spread spectrum programming bit(14:8) these spread spectrum bits in byte 12 and 13 will program the spread pecentage of pll. the user does not need to modify these settings unless non- standard spread amounts are required. the part defaults to - 0.5% spread when spread is enabled. -- - - - - - byte 13 - reserved byte 12 - spread spectrum programming bit(7:0) these spread spectrum bits in byte 12 and 13 will program the spread pecentage of pll. the user does not need to modify these settings unless non- standard spread amounts are required. the part defaults to - 0.5% spread when spread is enabled. -- - - - - the decimal representation of m and n divider in byte 10 and 11 will configure the pll vco frequency. default at power up = latch-in or byte 0 rom table. vco frequency = fxtal x [ndiv(9:0)+8] / [mdiv(5:0)+2]. the user does not need to program these resgisters for standard frequencies. -- - - - - - byte 11 - n divider programming byte11 bit(7:0) and byte10 bit(7:6)
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 16 indexarea 1 2 n d h x 45 e1 e seating plane a1 a e - c - b .10 (.004) c c l min max min max a -- 2.00 -- .079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 variations min max min max 28 9.90 10.50 .390 .413 10-0033 reference doc.: jedec publication 95, mo-150 0.0256 basic common dimensions in millimeters in inches common dimensions 209 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.65 basic 28-pin ssop package drawing and dimensions
idt ? four output differential frequency generator for pcie gen3 and qpi 1681c?08/26/10 9fg430 four output differential frequency generator for pcie gen3 and qpi 17 min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 de e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0035 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) indexarea 1 2 n d e1 e seating plane a1 a a2 e - c - b c l aaa c 28-pin tssop p acka g e dra wing and dimensions ordering information part / order number shipping packaging package tempera ture 9fg430aflf tubes 28-pin ssop 0 to +70c 9fg430aflft tape and reel 28-pin ssop 0 to +70c 9FG430AFILF tubes 28-pin ssop -40 to +85c 9FG430AFILFt tape and reel 28-pin ssop -40 to +85c 9fg430aglf tubes 28-pin tssop 0 to +70c 9fg430aglft tape and reel 28-pin tssop 0 to +70c 9fg430agilf tubes 28-pin tssop -40 to +85c 9fg430agilft tape and reel 28-pin tssop -40 to +85c ?lf? suffix to the part num ber are the pb-free conf iguration and are rohs com pliant. ?a? is the device revision designator (w ill not cor relate w ith the datasheet revision).
9fg430 four output differential frequency generator for pcie gen3 and qpi 18 innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt , ics, and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ?? revision history rev. issue date who description page # 0.1 7/13/2010 rdw new datasheet. a 7/13/2010 rdw release b 7/20/2010 rdw 1. added ppm tables to ds for both 25m and 14.318m inputs 2. added test load figures c 8/25/2010 rdw 1. updated/reformatted electrical tables 2. corrected features/benefits and general descript ion 3. updated pull up ^ and pull down v indicators. 4. updated termination figures to include fig. 5 fo r ref output, merged test load figures into these figures. 1, various

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